Carl McCrosky

Biography

I am retiring as of June 30, 2010. Consequently, I'm unable to accept any graduate students.

I have an M.Sc. (Computer Science, 1981) and a Ph.D. (Electrical Engineering, 1985) from Queens University of Kingston, Ontario. High-lights of my career, beginning in 1970, include: founding partner of Andyne Computing Limited (now part of Hummingbird Ltd.), Professor of Computer Science at the University of Saskatchewan from 1985 until 1998, founding partner and Chief Scientist of Hypercore Systems Limited (now part of PMC-Sierra Ltd.), and Principal Engineer with PMC-Sierra Ltd. from 1998 through 2004 (http://www.pmc-sierra.com).

I am presently teaching in a half-time position in Electrical Engineering at the University of Saskatchewan (http://www.engr.usask.ca/dept/ele). I hold an Adjunct Professorship with Telecommunications Research Labs (http://www.trlabs.ca).

I am partially retired, and spend my free time sailing my ocean-going sloop, kayaking the rivers and lakes of western Canada, boat building, playing the violin, bird watching, reading, making (sometimes) decent home-made wine, and a bit of photography (http://homepage.usask.ca/cdm518/).

Contact

E-mail:

Phone:

Location:

Research Projects

Next-Generation Transport Networks: enabling QoS, reducing management costs, simplifying protocol stacks and reducing hardware costs through a thorough re-thinking of transport network design.

Synthesis of Asynchronous Logic Circuits from Declarative Specification Languages.

Global Synchronization Primitives for Multi-Threaded Multi-Processors.

On-going research to support Salvador Dali's "paranoiac-critical method," defined as "a spontaneous assimilation of irrational knowledge based upon the critical and systematic objectification of delirious phenomena." "I believe," Dali predicted, "that the moment is near when by a procedure of active paranoiac thought, it will be possible . . . to systemize confusion and contribute to the total discrediting of the world of reality." {Clearly his plan is working - we're just trying to do our bit to help out.}

Collaborative Research

FANFARE Fall Prediction and Monitoring System, with colleagues at the Univ. of Sask.

Teaching

CME 433

Digital Systems Architecture http://www.engr.usask.ca/classes/CME/433/

This course begins by examining the architectures of the principle modes of implementation of complex digital systems: software, FPGAs, and custom VLSI systems. The second half of the course is taken up by a common design problem, in which the instructor takes on roles as the customer and the team leader, and the students work in varying teams to design some objective digital system.
This course is co-taught with Prof. Khan Wahid, who assumes responsibility for the first half while I take the second half.

CME 451

Transport Networks http://www.engr.usask.ca/classes/CME/451/

This course considers how Internet Protocol - the universal language of the Internet - is transported by underlying network layers. Current solutions (e.g. IP over ATM on SONET on fibre) are studied, and a variety of future alternatives are examined. The course focuses on the switching and queuing requirements imposed by varying protocol choices, and considers how the required switching network elements can be architected.

EE 391

Electrical Engineering Lab. II http://www.engr.usask.ca/classes/EE/391/
*not currently taught by McCrosky*

Laboratory experiments and exercises of design software packages for the corequisite courses.

CME 898

Multi-core Processors http://www.engr.usask.ca/classes/EE/391/
*not currently taught by McCrosky*

This was a special topics grad course taught in the fall of 2008 with Prof. D. Makarof of Computer Science.

Graduate Students

Dylan Griffiths; MSc

Tim Fretz; MSc

Former Graduate Students

Ghatraju, Lakshmikanth ("Kanth"); PhD

Jalnapurkar, Anant; PhD

Mukhopadhyaya, Utpal; PhD

Roy, Kanad; PhD 1995

Sailor, Ken; PhD 1993

Wang, Lei; PhD

Wang, Yuke; PhD 1995

Ackerman, Kevin; MSc

Ai, Jun; MSc

Callele, David; MSc

Chen, WangXiang; MSc

Chen, Xiaoshu; MSc

Deng, Zheng; MSc

Dutta, Diptendu; MSc

El Gebaly, Hani; MSc

Epsilon, Raja; MSc

Fernandes, Henry; MSc

Gammo, Louay; MSc

Ghavamnia, Mohammad; MSc

Guo, Qingrong; MSc

Gyawali, Umesh; MSc

Hichri, Haikel; MSc

Hoeber, Orland; MSc

Hughes, Andrew; MSc

Jain, Kavita; MSc

Katikaneni, Nanda; MSc

Komarla, Eshwari Prasad; MSc

Kuang, Tianbo; MSc

Li, Weidong; MSc

Luo, Jingxiang; MSc

Mukhopadhyaya, Utpal; MSc

Roshan Parajuli; MSc

Reid, Irving; MSc

Rolheiser, Nick; MSc

Roy, Kanad; MSc

Sailor, Ken; MSc

Shi, Fang; MSc

Shi, Weiqun; MSc

Shukla, Monisha; MSc

Sinha, Hemant; MSc

Sud, Pankaj; MSc

Takaya, Norif; MSc

Tandri, Sudarsan; MSc

ven der Buhs, Brian; MSc

Wan, Zhihui; MSc

Wang, Lei; MSc

Xing, Anqing; MSc

Xu, Yanbing; MSc

Selected Journal Papers Copyright Infomation

[22]	Yuke Wang, C. McCrosky, and X. Song, "Single-faced Boolean functions and their minimization", The Computer Journal, Vol. 44, No. 4. pp. 280-291, April 2001.
[21]	Alpesh Patel, Anthony J. Kusalik, Carl McCrosky: Area-Efficient VLSI Layouts for Binary Hypercubes. IEEE Trans. Computers 49(2): 160-169 (2000)
[20]	Yuke Wang, Mostafa Abd-El-Barr, and Carl McCrosky, An Algorithm for Total Symmetric OBDD Detection, IEEE Trans. on Computers 46(6), pp 731-733, 1997.
[19]	Wang, Lei and McCrosky, Carl, An approximate solution for queuig network models of a burst-level traffic control scheme in ATM WAN, Performance Evaluation 34(3), pp 125-145, 1998.
[18]	Yuke Wang and Carl McCrosky, Solving Boolean Equations Using ROSOP Forms, IEEE Trans. on Computers 47(2), pp 171-177, 1998.
[17]	"Adaptive Rate Subscriber Loop Data Transmission with Ethernet Interfaces", Journal of Circuits, Systems and Computers, Vol. 7, No. 4, pp. 273-281.
[16]	Wang and C. McCrosky, "Negation Trees: A Unified Approach to Boolean Function Complementation", IEEE Trans. on Computers, 45(5): 626-629, 1996.
[15]	Zhu, Abd-El-Barr, and C. McCrosky, "A New Theory for Testability- Preserving Optimization of Combinational Circuits", VLSI Design, 5(1), 1996, pp. 59-75.
[14]	Li, Abd-El-Barr, and C. McCrosky, "D-CPT: A Time/Space Efficient Fault Simulator", International Journal of Electronics 76 (4), pp. 633-645.
[13]	Sailor and C. McCrosky, "A Practical Approach to Type-Sensitive Parsing", Computer Languages 20 (2), pp. 101-116.
[12]	Xu, Abd-El-Barr, and C. McCrosky, "Graph-Based Output Phase Assignment for PLA Minimization", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 14(5), pp. 1-10.
[11]	C. McCrosky, and Ken Sailor, "A Synthesis of Type-Checking and Parsing", Computer Languages Journal, 18(4), 1992, pp. 241-250.
[10]	S. Tandri, M. Abd-El-Barr, C. McCrosky, "Integrated Specification, Simulation, and Fabrication of Systolic/Wavefront Arrays", International Journal of Computer-Aided VLSI Design, 1(3), 1991, pp. 273-290.
[9]	C. McCrosky, "Intermediate Container Removal", Computer Languages Journal, 16(2), 1991, pp. 179-195.
[8]	M.A. Jenkins, J. Glasgow., C. McCrosky, and H. Meijer, "Expressing Parallel Algorithms in Nial", Parallel Computing, 11, 1991, pp. 331-347.
[7]	C. McCrosky and D. Dutta, "A Type-Theoretic Semantics of Arrays", Applied Math. Letters, 3(1), 1990, pp. 83-87.
[6]	C. McCrosky, "Message Routing in Synchronous Hypercubes", Computer Systems Science and Engineering, 4(1), 1989, pp. 89-96.
[5]	C. McCrosky, "Realizing the Parallelism of Array-Based Computations", Parallel Computing 10, 1989, pp. 29-43.
[4]	C. McCrosky and M.A. Jenkins, "Design of a Processor for Array- Theoretic Computation", Journal of Systems and Software, 9(1), 1989, pp. 67-74.
[3]	C. McCrosky and B. ven der Buhs, "On the Design of On-Chip Instruction Caches", Journal of Microprocessors and Microsystems, 12(10), 1988, pp. 563- 572.
[2]	M.A. Jenkins, J. Glasgow, and C. McCrosky, "Programming Styles in Nial", IEEE Software, 3(1), 1987, pp. 46-55.
[1]	D. Athersych, D. Barnard, G. MacEwen, C. McCrosky, and D. Ross, "A Comparative Evaluation of Ada and Euclid", INFOR, 21(3), 1983, pp. 157- 176.

Conference Publications Copyright Infomation

[29]	Kevin Ackerman, David E. Dodds and Carl McCrosky, 2005, "Protocol to Avoid Noise in Power Line Networks", Proceedings of International Symposium on Power Line Communications and its Applications, April 6-8, Vancouver, Canada, pp. 181-185.
[28]	Mostafa H. Abd-El-Barr, Yanging Xu, Carl McCrosky: Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits. Great Lakes Symposium on VLSI 1999: 388
[27]	Lei Wang, Carl McCrosky: Performance Comparison of Control Schemes for ABR Service in ATM LANs. MASCOTS 1997: 205-212
[26]	N. Takaya, D.E. Dodds and C.D. McCrosky, 1997. "Adaptive Rate Subscriber Loop Data Transmission with Ethernet Interfaces", Journal of Circuits, Systems and Computers, Vol. 7, No. 4, pp. 273-281.
[25]	Xing and C. McCrosky, "Switch Performance with Self-Similar Traffic", Third Workshop on Performance Modelling and Evaluation of ATM Networks, pp.22/1 - 22/9, Ilkley, UK, 1995.
[24]	Wang and C. McCrosky, "Self-Similarity of Aggregated Network Traffic Models", Third Workshop on Performance Modelling and Evaluation of ATM Networks, pp. 738/1 - 38/13, Ilkley, UK, 1995.
[23]	Mukhopadhyaya and C. McCrosky, "New Modelling Techniques for Parallel Distributed ATM Switches", Third Workshop on Performance Modelling and Evaluation of ATM Networks, pp. 74/1 -74/10, Ilkley, UK, 1995.
[22]	Roy and C. McCrosky, "Transformation of Functional Specifications of Finite Difference Methods to Parellel Distributed Codes", PACT'95, Cyprus, 5 pages.
[21]	El-Gebaly, Abd-El-Barr, and C. McCrosky, "Architectural Trade-offs in Reduced Instruction Set Computers: A Case Study", IEEE Pac-Rim Conference, pp. 78-81, Victoria, B.C., 1995.
[20]	Jalnepurkar, C. McCrosky, and Wood, "Parallel Waveform Relaxation on Distributed Memory Computers", CA '94: Parallel Computing and Transputors Conference, 8 pages, Wollongong, 1994.
[19]	Ghatraju, Abd-El-Barr, and C. McCrosky, "High-Level Synthesis of Digital Circuits by Finding Fixpoints", European Design and Test Conference, pp.94-98, Paris, 1994.
[18]	Y. Xu, M. Abd-El-Barr, C. McCrosky, "A Deductive Method for Simulating Transistor Stuck-Open Fault Models in CMOS Circuits", European Test Conference (ETC'93), 14 manuscript pages, Rotterdam, April 1993.
[17]	Weidong Li, Carl McCrosky, Mostafa H. Abd-El-Barr: Reducing the Cost of Test Pattern Generation by Information Reusing. ICCD 1993: 310-313
[16]	W. Li, C. McCrosky, M. Abd-El-Barr, "On the Design and Analysis of Unmatched LFSR Pattern Generators in Pseudorandom Testing", European Design Automation Conference (EDA'93), 12 manuscript pages, Paris, Feb. 1993.
[15]	C. McCrosky, K. Jain, I. Reid, "Integration of Telecommunications Switching on SCS Hypercube Packet Switches", IEEE WESCANEX'93, pp. 150-153, Saskatoon, May 1993.
[14]	A. Jalnapurkar, C. McCrosky, Wood, H., "Simulation of MOS VLSI Circuits Using Parallel Processors", IEEE WESCANEX'93, pp. 171-176, Saskatoon, May 1993.
[13]	C. Vaidyanathan, D. Callele, C. McCrosky, "An Overview of a Fault Tolerant Communications Network", IEEE WESCANEX'93, pp. 177-183, Saskatoon, May 1993.
[12]	C. McCrosky, K. Roy and K. Sailor, "Falafel: Arrays in a Functional Language", Montreal Workshop on Arrays, Functional Programming and Parallelism, Montreal, 1990, 12 pages.
[11]	S. Tandri, M. Abd-El-Barr, and C. McCrosky, "High Level Specification, Simulation, and Fabrication of Systolic Arrays - A Case Study", The 1990 Canadian Conference on VLSI, Ottawa, 1990, pp. 100-107.
[10]	C. McCrosky, and A. Kusalik, "Improving First-Class Array Expressions Using Prolog", IEEE International Conference on Logic Programming, Seattle, 1988, pp.18-25.
[9]	C. McCrosky, "The Elimination of Intermediate Containers in the Evaluation of First-Class Array Expressions", IEEE International Conference on Computer Languages, Miami, 1988, pp. 134-142.
[8]	J. Glasgow, M.A. Jenkins, C. McCrosky, and H. Meijer, "Expressing Parallel Algorithms in Nial", Proc. Twentieth Annual Hawaii Int. Conf. on Systems Sciences, Hawaii, 1987, pp. 200-211.
[7]	C. McCrosky, and M.A. Jenkins, "ACE: The Array-Theoretic Computational Engine", Hawaii International Conference for System Sciences (HICSS-19), Honolulu, Hawaii, 1986, pp. 117-123.
[6]	M.A. Jenkins, J. Glasgow, and C. McCrosky, "Programming Styles in Nial", HICSS-19, Honolulu, Hawaii, 1986, pp. 267-275.
[5]	C. McCrosky, and M.A. Jenkins, "Communicating State Machines: A Design Methodology for VLSI Microprocessors", International Conference on Computer Design (IEEE/ICCD), Port Chester, NY, 1985, pp. 732-735.
[4]	J. Glasgow, M.A. Jenkins, and C. McCrosky, "User Defined Parallel Control Strategies in Nial", IEEE Symposium on Logic Programming, Boston, 1985, pp. 172-179.
[3]	C. McCrosky, J. Glasgow, and M.A. Jenkins, "Nial: A Candidate Language for Fifth Generation Computing Systems", Proceedings of the ACM Annual Conference, San Francisco, 1984, pp. 157-166.
[2]	C. McCrosky, "Education-on-Demand", extended abstract in Multimedia to the Home, Regina, Aug. 1993.
[1]	C. McCrosky, J. Glasgow, and M.A. Jenkins, 1984. "Nial: A Candidate Language for Fifth Generation Computing Systems". IBM Joint Study Conference, Ft. Lauderdale, Florida (one paper was written for the ACM Annual Conference (1984). It was invited for presentation at the IBM conference, and published in separate proceedings).

Books / Chapters in Books

[4]	K. Iniewski, C. McCrosky, D. Minoli "Network Infrastructure and Architecture", Wiley, 542 pgs, 2008.
[3]	C. McCrosky and Yuke Wang, "Boolean Functions", in Encyclopedia of Electrical and Electronics Engineering, John Wiley & Sons, Inc., Edited by John Webster, December 1997., pp 508-530, 1999.
[2]	C. McCrosky, J. Glasgow and M.A. Jenkins, 1988. "Nial: A Candidate Language for Fifth Generation Computing Systems", in Expert Systems - Microcomputer Based Systems, Gupta and Prasad ed., IEEE Press, 1988, 18 pages.
[1]	J. Glasgow, M.A. Jenkins, and C. McCrosky, "User Defined Parallel Control Strategies in Nial", in Expert Systems - Microcomputer Based Systems, Volume II, Gupta and Prasad eds, IEEE Press, 1988, 27 pages.

Patents

[18]	USA 6,741,552 B1; Fault-Tolerant, Highly-Scalable Cell Switching Architecture; Carl McCrosky, Jeff Roe, Ian Barrett, and Ken Sailor; issued May 25, 2004; assigned to PMC-Sierra Inc.
[17]	USA 6,820,159 B2; A Bus Interface for Transfer of Multiple SONET/SDH Rates over a Serial Backplane; Winston Mok, Steven Lang, Carl McCrosky, and Richard Tse; issued Nov. 16, 2004; assigned to PMC-Sierra Inc.
[16]	USA 6,870,831 B2; Flexible, Self-Aligning Time and Space Switch Fabrics Andrew Hughes, Carl McCrosky, et al.; March 22, 2005; assigned to PMC-Sierra Inc.
[15]	USA 6,876,650 B2; Bipartite graphical connection scheduling in time and space switch fabrics McCrosky, et al.; April 5, 2005; assigned to PMC-Sierra Inc.
[14]	USA 7,391,787 B1; System and Method for Opportunistic Request-Grant Switching; Carl McCrosky; assigned to PMC-Sierra Inc.
[13]	USA 7,417,985 B1; An Egress Selection Switch Architecture with Power Management for a Time Division Multiplexed Memory Switch; assigned to PMC-Sierra Inc.
[12]	USA 7,492,760 B1; Memory Egress Self Selection (MESS) Architecture; Winston Mok, Carl McCrosky, et al.; assigned to PMC-Sierra Inc.
[11]	USA 7,593,411; Bus interface for transfer of multiple SONET/SDH rates over a serial backplane August 22, 2002; assigned to PMC-Sierra Inc.
[10]	USA Application in progress; Multiple Tenancy Cut-Through Switching of Fibre Channel Arbitrated Loops; Carl McCrosky et al.; assigned to PMC-Sierra Inc.
[9]	*************************************************************************** Items below this line are industrial VLSI products architected by McCrosky
[8]	"TSE/TBS" 40Gb/s SONET STS-1 Switching Architecture, developed as a commercial product for PMC-Sierra.
[7]	"NSE/SBS" 20Gb/s SONET DS0/VT Switching Architecture, developed as a commercial product for PMC-Sierra.
[6]	"TSE-160/TBS-9953" 160Gb/s SONET Switching Architecture, developed as a commercial product for PMC-Sierra.
[5]	"TSE-240" 240Gb/s SONET Switching Architecture with hardware SONET protection, developed as a commercial product for PMC-Sierra.
[4]	"TSE-Nx160" 640Gb/s SONET Switching Architecture, developed as a commercial product for PMC-Sierra.
[3]	"WSE-40" 40Gb/s SONET VT Switching Architecture with hardware SONET protection, developed as a commercial product for PMC-Sierra.
[2]	"RSE" 256Gb/s sRIO Switching Architecture, developed as a commercial product for PMC-Sierra.
[1]	"CTS-20x4G" 80Gb/s Fibre Channel Switching Architecture, developed as a commercial product for PMC-Sierra.